The present invention relates to methods of testing microprocessors. More specifically, the invention relates to methods of loading a test program into a microprocessor's internal caches and then controlling the execution of that program. The methods involve controlling the microprocessor's clock in a manner that allows a program's memory content to be efficiently shifted onto the microprocessor's pins and then loaded to the microprocessor's instruction and data caches.
During development of a microprocessor, it is necessary to extensively test for performance and bugs. Early in development, the microprocessor exists only as a software design specifying the device's Boolean logic (typically in a hardware design language such as Verilog). At this stage, various tests (collectively referred to as "design verification") may be performed on the microprocessor design. After a particular design is found acceptable, it is converted from software to hardware through a series of steps culminating in "tape out."0
Even though the hardware design language version of the microprocessor may have been extensively tested for performance and bugs during design verification, it is possible that errors were introduced during the process of converting the software microprocessor to the hardware microprocessor. Moreover, design verification may not cover all aspects of possible microprocessor operations. Thus, it is necessary to extensively test the silicon version of the microprocessor before it is ready for market introduction.
Various testers have been developed for this purpose. Two exeplary testers are the Polaris series VLSI testers available from Megatest of San Jose, Calif. and the Sentry series of testers available from Slumberger of San Jose, Calif. Such testers typically operate very fast but require connections to many of the microprocessor's pins (which typically number in the hundreds). Thus, testers typically are also very expensive. As a general rule, each pin on a tester adds $10,000 to the tester's total cost. Thus, there is a strong incentive to use testers having smaller numbers of pins.
The IEEE 1149.1 Standard--also referred to as JTAG (for Joint Task Action Group)--allows five dedicated pins to be used to access all pins on an integrated circuit chip. The JTAG standard architecture and methodology is described in the document "IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE Standard 1149.1-1990 which is incorporated herein by reference for all purposes. As will be explained in more detail below, a JTAG interface can be employed to load bit values on each pin of microprocessor by sequentially feeding these values through a single JTAG pin (the TDI pin) and shifting the bits along the perimeter of the microprocessor as a chain from pin-to-pin (a "boundary scan shift operation"). Ultimately, after the number of bits fed through the TDI pin equals the number of boundary scan cells (there is at least one boundary scan cell for each microprocessor pin) on the microprocessor, the bit values are in the correct locations on the microprocessor pins. At this point, the microprocessor is in a state which may be further tested as desired by the end user.
At least one microprocessor test system has employed the JTAG interface to load data on the pins of a device being tested. This system, which is provided on the SuperSPARC microprocessor available from Sun Microsystems of Mountain View Calif., allowed a user to load certain test programs into the microprocessor's onboard caches via an IEEE 1149.1 interface (JTAG) and execute them at the full functional clock rate. It also allowed a user to command the processor to temporarily halt execution of the normal instruction stream. Once halted, the user could direct the processor to execute any normal SPARC instruction (i.e., assembly language instructions for the SuperSPARC microprocessor) via the IEEE 1149.1 interface. The user could also resume the halted execution after performing the desired emulation functions. Unfortunately, the complex logic required for these functions represented a significant amount of area (on the SuperSPARC microprocessor) and worsened some critical timing paths. What is needed therefore is a system and methodology which provides the functionality of the above-described SuperSPARC test system without introducing substantial complexity to the microprocessor or interfering with the microprocessor's normal functioning.